Study on the Effect of Film Process on Interface and Interconnection Reliability in the TSV Structure

The through silicon via (TSV) is a critical technology to provide short vertical interconnects for 2.5D/3D advanced packaging. But the large mismatch of thermal expansion coefficient (CTE) between Cu and Si/SiO2 results in thermal stress that compromises the thermal mechanical reliability of TSV structures. In this study, the defects caused by thermal stress during film process were investigated by Focused Ion Beam (FIB). Through the Finite Element Analysis (FEA), we have assessed the influence of the liner layer thickness
$(\text{THK}_{\text{liner}})$
between Cu and Si and the interlayer dielectric thickness
$(\text{THK}_{\text{ILD}})$
, on the induced thermal stress. Our study elucidates the interplay between the
$\text{THK}_{\text{liner}},\text{TRK}_{\text{ILD}}$
and thermal stress, confirming that these parameters significantly reduce thermal stress when the THK
liner
is set to approximately
$0.4\mu \mathrm{m}$
and the
$\text{THK}_{\text{ILD}}$
to around
$1\mu \mathrm{m}$
. These dimensions are thereby identified as the optimal process parameters for stress minimization. This work can provide an important technical means for the manufacture of TSV with high interface and interconnected reliability, and provide an important reference for practical engineering problems in the high density 2.5D/3D integration.