High-density embedded silicon fan-out (H-eSiFO) process for a CMOS operational amplifier

Embedded Silicon Fan-out (eSiFO) packaging is considered one of the ideal advanced packaging technologies due to its suitability for heterogeneous integration and its exceptional electrothermal performance. This study employed the H-eSiFO process to package a CMOS operational amplifier chip, analyzing the impact of various packaging process steps such as chip thinning and dicing, surface passivation, and the fabrication of the redistribution layer on chip performance. A corresponding test circuit was designed for the packaged chip to conduct functional performance tests. The results indicate that this packaging method does not adversely affect the chip's performance, demonstrating the potential of H -eSiFO in the advanced packaging of Chiplet.