Effects of 2.5D/3D Stacking Structure on Signal Integrity of Chiplet Interconnection

In the post-Moore era, the chiplet technology based on advanced packaging would be a quite promising solution for the high-performance AI chips. The chiplet technology with 2.5D/3D stacking package architecture transforms traditional on-chip interconnection into chip-to-chip (C2C) interconnection. The C2C interconnection usually comprised of through-silicon-via (TSV), metal wiring (RDL) and bonding bumps with varying structures, sizes, materials and spatial layout, which could affect the signal integrity of the C2C channel. To further develop the chiplet technology, quantitatively evaluating the signal integrity performance of C2C interconnection in chiplet 2.5D/3D packages is very important. In this paper, the effects of C2C interconnect structures (RDL, TSV, bump) and their related parameters (size, pitch, and number of stacked layers) on signal integrity were investigated by simulations with HFSS and ADS tools. The simulation results show that the thickness of the dielectric layer between the RDL significantly affects the signal transmission capability of the channel. Besides, as the TSV spacing increases, the S11 and S21 of the channel are gradually improved, but the crosstalk is likewise increased. In combination with the optimized design parameters, the S21 of the 1650 μm long 5-layer stacked C2C interconnection channel is better than -4.1 dB in the 56 GHz range, but the S11 is above -20 dB after 17 GHz, which can be attributed to the impedance discontinuities in the complex C2C interconnection structure. This work reveals the signaling capabilities of the RDL-TSV-bump interconnection, which can provide a reference for chiplet 2.5D/3D packaging design.