In-Situ Observation and Thermo-Mechanical Stress Analyses of Flip Chip Reflow Process via SEM-DIC Coupled Method

The reliability of Flip Chip package is often compromised due to cracks in-between chips and underlying electronics, especially pre-solder and solder resist cracks, observed during the reflow process. These failures primarily caused by the mismatch in the coefficients of thermal expansion (CTE) between different materials, which cause the critical stress in intermetallic compounds on the copper pad layer and solder bump. Though failure and crack at bump are critical for Flip Chip package, the fracture mechanism of bump crack is still not well understood, and the resulting mechanical behaviors are even more complicated. To build a better understanding of the failure, this study introduces an innovative approach that combines Digital Image Correlation (DIC) and Scanning Electron Microscopy (SEM) for in-situ observation and quantitative characterization of the Flip Chip reflow process. Using a miniature heat loading platform in SEM, we track the sample as the temperature changing and further determine the strain field evolution via DIC. The result indicates that strain and stress concentrations primarily occur at the solder bumps edge leading to delamination and potential crack initiation. Large strain and hence stress field is also observed in the Y direction within the polyamide layer which leads to a potential failure risk. This detailed analysis provides insights into the thermal-mechanical stress distributions, ultimately aiming to improve the reliability of Flip Chip packages during thermal reflow tests.