Analysis and Optimization of Equivalent Source Inductance for Balancing Dynamic Current of Multi-Chip SiC Power Modules Based on Cu-Clip Bonding

In recent years, the surge in global energy demand coupled with a growing focus on environmental protection and the enhancement of energy efficiency has exposed the physical limitations of traditional silicon-based power semiconductor devices. The adoption of multi-parallel chip configurations has become essential to boost the module's current capacity. Nonetheless, layout asymmetry in multi-parallel SiC modules can lead to disparities in parasitic inductance among chips, further causing uneven current distribution. To address the challenge of uneven parallel current distribution, this study delves into the mechanisms of self-inductance and mutual inductance among current paths, deriving a dynamic current equilibrium equation based on magnetic coupling effects and equivalent inductance. This equation serves as a theoretical foundation for optimizing dynamic current distribution among parallel chips. Leveraging this equation, the structure of the Cu-clip is optimized to reduce current non-uniformity from 55% to 16%. Additionally, by employing finite element software to extract parasitic parameters from two different module layouts, a double-pulse simulation model incorporating each current segment's self-inductance and mutual inductance is developed. The discrepancy between simulation and actual measurements is a mere 2%, underscoring the model's accuracy.