Simulation Studies of Hygro-Thermal-Vapor Induced Stresses and Interface Delamination in High Bandwidth Memory (HBM) Package With Different Numbers of Stacked Chips During Reflow Process

In recent times, there has been a pressing need for research and development (R&D) initiatives aimed at improving the reliability, endurance, and cost efficiency of high bandwidth memory (HBM). This necessity arises from the escalating demand for sophisticated applications like high-performance computing (HPC) and artificial intelligence (AI). Within the realm of reliability concerns, issues pertaining to package damage and failure resulting from the absorption of moisture by polymer materials have gained significant prominence. This investigation involves the development of finite element models depicting stacked DRAM chips with various layer counts (N=2, 4, 8, 12, 16, and 20). The chips undergo preconditioning treatment at 85°C/85% relative humidity (RH) with a duration of 168 hours, followed by reflow to ascertain the distribution of moisture concentration. To examine moisture diffusion during the reflow process, the so-called internal source method is adopted. Considering the hygro-thermal-vapor loads, the distribution of von Mises stress at the peak reflow soldering temperature is determined. The findings of the simulations indicate that the moisture content within the package is not fully saturated post-preconditioning. Moreover, the region of unsaturation expands with an increase in the number of stacked chip layers, except for an unusual decline observed at N = 20. Throughout the reflow process, moisture desorption occurs rapidly. Nonetheless, a substantial amount of moisture persists within the HBM package at the final phase of reflow process, leading to the generation of saturated vapor pressure, thereby facilitating interfacial crack propagation and delamination. In HBM packages subjected to hygro-thermal-vapor loads, the topmost or bottommost chips exhibit heightened susceptibility to cracking and delamination.