The Reverse Bias Reliability of SiC MOSFET Under Different Conditions and Failure Analysis

SiC MOSFET typically require a gate voltage below −5V for a complete channel close due to the inherent characteristics. In practical applications, when SiC MOSFET is turned off, it needs to withstand a negative gate voltage, while subjecting to a high bus voltage at the same time. The negative gate voltage need to be considered when studying the reverse-bias reliability of SiC MOSFET. At present, few literatures study the reverse-bias reliability of SiC MOSFET between zero gate voltage and negative gate voltage. Existing standards require that the gate and source of the device be shorted during HTRB test. However, the HTRB test at negative gate voltage is abler to investigate the voltage tolerance of SiC MOSFET in practical applications. In this paper, the HTRB test at zero gate voltage and negative gate voltage is carried out to study the reverse-bias reliability of 1200V,
$25\mathrm{m}\Omega$
SiC N-channel device, and the failure mechanism is analyzed. The results show that the differences in the reverse-bias reliability at different gate voltages have not been found yet since the test start, and the high temperature caused by the high power consumption generated by the leakage current creates a hot spot on the chip surface and causes a short circuit on the device.