Investigation on Wafer Heterogeneous Bonding Process and Performance of CMOS Integrated Circuit on Silicon Carbide Substrate

CMOS integrated circuits (ICs) were heterogeneous bonded to semi-insulating 4H-SiC wafer by using SOI or Si wafers that have completed 0.18 μm CMOS processing technology. Prebonding and debonding processes were used to remove the Si handle layer and SiO2 layer for SOI IC wafer, to thin the Si substrate for Si IC wafer. Through back grinding, the thickness of the initial SOI and Si CMOS wafer were 7 μm and 20 μm, respectively. Benzocyclobutene (BCB) was uesd as the bonding interface layer for SOI IC wafer due to the extremely thin CMOS thickness of 7 μm, and directly bonding was realized for Si IC with interface layer about 10 nm. The square resistance and off-state leakage current increase with the ambient temperature improving from 25 °C to 175 °C, which is more obvious for SOS devices than SOI devices because of the high thermal resistance of BCB interface layer. For comparison, the electrical properties of directly bonded SOS Operational Amplifier (OPA) are basically consistent with those of Si OPA. The Vos, f
−3dB
and SR of SOS OPA are -16 μV, 90 kHz, and 0.346 V/μs, respectively. This study provides a practical method to realize SOS CMOS IC, boosting the further exploration, thermal advantage and high-performance development of Si on SiC IC chips.