Compact Spatially Symmetric Double-Sided Embedded Packaging Method for Parallel SiC MOSFETs

This paper proposes a compact spatially symmetric double-sided cooling packaging method with the aim of enhancing the parallel current-sharing capability of SiC MOS-FETs while fully exploiting their inherent advantages in high-frequency and high-temperature performance. Firstly, this packaging method utilizes a spatially symmetric layout to achieve complete symmetry in parasitic parameters and thermal resistance of parallel SiC MOSFET chips, thereby enhancing the parallel operation capability of the devices. Furthermore, the compact structure reduces the main power switching loop parasitic inductance to 1.8 nH, while the use of high-thermal-performance materials and the implementation of a double-sided heat dissipation path reduce the junction-to-cover thermal resistance to below 0.058 °C/W. These advancements facilitate the optimal utilization of the SiC MOSFET chips' high-temperature and high-frequency capabilities. Moreover, spatially symmetric terminal lead-out method enables the measurement of parallel characteristics for the parallel-connected chips, providing a tool for the study of parallel characteristics in power semiconductor devices. The effectiveness of this packaging method is validated through double-pulse experiments.