Finite Element Analysis of the Sintered Layer and Buffer Layer on SiC Module Reliability

Thermal fatigue failure is a key issue that affects the long-term reliability of silicon carbide (SiC) power modules. It is urgent to select appropriate packaging materials to release the thermal mismatch between module layers. However, packaging using traditional sintered layer solder cannot meet the demands of module reliability under high power density working conditions. In this paper, the effect of the sintered layer with a novel nano-silver (Ag) solder on the reliability of SiC power modules is investigated by using the finite element analysis (FEA) method. Simulation results of thermal-mechanical modeling under power cycling conditions show that increasing the thickness of the Ag sintered layer can effectively reduce the thermal stress of the module without affecting the chip junction temperature. Moreover, the effect of introducing a molybdenum buffer layer on releasing module stress and improving module lifetime is further explored.