Design and Modeling of Non-Uniform through-Glass Vias and its Optimization Methods

In this study on 3D ICs with glass substrates, we address the challenges of non-uniform TGVs causing signal delay and loss, especially in high-frequency circuits. We introduce a method to calculate parasitic RLGC parameters for these structures, using a Gaussian function to model sidewall roughness and enhance parameter precision. Findings show that higher tapers and roughness increase losses and delays. Validation samples fabricated via laser bonding and tested up to 40 GHz confirm the accuracy of our calculations. Additionally, by controlling the laser-induced wet etching (LIWE) process, we effectively optimize the sidewall roughness of TGVs, significantly reducing it from 2.7 µm to 32 nm.