Multi Gigabit Digital Modulator for Satellite Implemented based on JESD204B protocol

This paper presents the design and implementation aspects of JESD204B protocol based multi-gigabit digital modulator for satellite to ground data transmission link. The paper brings out the complexity and challenges involved in the design. This digital modulator comprises of RF-sampling digital to analog converter, FPGA, clock-module for synchronization and power distribution network. Apart from the hardware design, the paper discusses the software aspects of instantiating the JESD204B IP core to maximize the achievable data rate. The design supports multiple modulation schemes-QPSK, 8PSK, 16APSK and offers flexibility in terms of programmable data rates, programmable IF frequency using the same hardware.