A 4×6.25-Gbps Serial Link Transmitter Core in 0.18-μm CMOS for High-Speed Front-End ASICs

High-speed serial link transmitters have been widely integrated in front-end ASICs. However, it’s difficult to achieve high data bandwidth, low power consumption and low jitter at the same time. In this paper, a 4×6.25 Gbps serial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18-μm CMOS technology. The core consists of a common ring-oscillator based PLL and four individual transmitter channels. Each channel contains a two-stage 20:2 serializer, a two-tap half-rate feed-forward equalizer and a clock manager circuit. With a new architecture of the final-stage serializer and half-rate feed forward equalizer, and an optimized selection scheme of the flip-flops in the serializer, the number of CML devices is decreased and the total power consumption is significantly reduced compared with previous works, while maintaining high data bandwidth and low jitter. To validate the designed transmitter core, a prototype chip has been fabricated and tested. The Test results show that the transmitter core operates from 3.5 to 6.75 Gbps. At a data rate of 6.25 Gbps, the PLL outputs a 3.125 GHz clock, with a phase jitter of 1.006 ps RMS, and the total jitter of the output data is 45.5 ps at a bit error rate of 1×10
^-12
. The core occupies an area of 0.44 mm
²
and consumes 27.8 mW/Gbps at a 1.8 V supply.