DCIM Compiler - Physical Design Generator

Accuracy and precision requirements in machine learning applications ranges from low precision tasks like Binary Neural Network inference to highly precision floating-point number weight training. The varying specifications have led to many directions in machine learning acceleration. The Compute-in-Memory (CIM) paradigm initially developed for low precision machine learning tasks in analog domain has recently extended into digital domain in support of higher accuracy and precision Vector-Matrix-Multiplication (VMM) operation. To cope with various applications, a fully automated process of designing and implementation of custom DCIM (Digital Compute-in-Memory) circuits is therefore highly desirable. This paper presents the design of a DCIM-compiler that can be used to generate physical design of a customizable DCIM macrocell. To achieve an energy and delay optimized DCIM design, a major design effort is the large adder tree circuits. Since most efficient adder tree structures are irregular, the physical design of the corresponding CIM cannot be simply constructed by mosaic instantiation of cells; a technique commonly uses in regular SRAM compilers. The presented DCIM-compiler combines and automates adder tree construction, schematic design, circuit synthesis and place & route process in a coordinated flow that produces DCIM physical design, according to the user specifications; and optimized for area, power, and performance.