Non-Ideal Reset in Incremental Delta-Sigma ADCs

The working principle of an ideal incremental Delta-Sigma (I-DS) converter is based on memoryless operation between successive Nyquist samples. This concept allows I-DS converters to achieve a high resolution single-shot conversion without any inter-sample interference. The underlying theory assumes ideal resetting of the internal states of the loopfilter and the reconstruction filter. With non-ideal switching, memoryless operation is not achieved anymore. In practice, any reset switch is non-ideal with large variation over process, voltage and temperature, and its design is based on a parametric sweep simulation until the required resolution is achieved. Alternatively, more time is spent for the reset. This is as the state of the art does not present an analysis on the impact of non-ideal reset on the performance of I-DS modulators. In this paper, the non-ideal memory in the loopfilter due to non-ideal reset is investigated with respect to its dependency on input signal and quantization-noise. An analysis then presents a closed theory to calculate the reset-switch on-resistance and reset-pulse duration with respect to a specified resolution.