LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching

In recent years, cryogenic silicon electronics have gained increased interest for applications in fields such as quantum computers and space exploration. Unfortunately, commercial technologies lack cryogenic compact models for circuit design. In this paper, we target the sizing of the critical input stage of a power efficient low-noise amplifier working at 7 GHz and 4 K with simultaneous noise and power matching for meeting the stringent specifications of a gate-dispersive readout circuit for spin quantum bits. In the absence of a compact model for the transistors in 28 nm FD-SOI technology, we propose a design methodology using a look-up table that has been buit with 4 K DC measurements of technology transistors and their associated capacitors to demonstrate the feasibility of the circuit.