Design Techniques for Sample-and-Hold with Bootstrapping in Low-Power SAR ADC

This paper investigates the errors of sample-and-hold (S/H) with bootstrapping in low-power SAR ADC. We show charge injection errors are of common-mode characteristics mainly and their impact is largely suppressed via differential signaling. We further show errors caused by bootstrapping voltage feed-through have both common-mode and differential-mode components. The impact of the former is suppressed by differential signaling while the latter doubles. Moreover, the loss of bootstrapping voltage due to the use of nMOS bootstrapping capacitors and the impact of the size of bootstrapping nMOS capacitors on bootstrapping voltage are investigated. Furthermore, we show errors caused by the voltage drop of sampling switches are of differential characteristics and double with differential signaling. The impact of supply voltage reduction on the voltage drop of sampling switches is also studied. We show the lower the supply voltage, the worse the voltage drop of sampling switches. Finally, we show errors caused by the voltage drop of sampling switches are most critical and can be reduced by increasing the size of sampling switches without sacrificing charge injection errors. These findings are verified using the simulation results of a differential S/H designed in TSMC 130 nm with a reduced supply voltage of 0.8 V.