FEA-Driven Solutions to Minimize Driving Loop Inductance and EMI in MHz PCB Designs

The gate driver parasitic loop inductance and EMI characteristics of a 1-MHz, 1-kW GaN buck converter are investigated. The parasitic effects contributed by PCB traces are critical in higher-power and MHz-frequency operational systems. These parasitic inductances lead to voltage overshoots and ringing, which is a primary cause of EMI. Therefore, the power and driving loops within the layout were designed to minimize loop inductances. The parasitic inductances, extracted through finite element analysis (FEA) tools, were modelled within LTspice to assess the impacts of the designed layout. The gate-to-source voltage waveform from the hardware exhibits slightly higher voltage spikes compared to the LTspice simulation. The conducted noise measured in the FEA was over the standard electromagnetic compliance limit by 10 dBuV in the frequency range of 1 MHz to 5 MHz. Adding a filter to the input side of the converter will improve the conducted emissions.