A Simply Design Method for CLLC Resonant Converter With Parasitic Capacitance

Switching transistors typically have parasitic capacitance. Existing research methods for CLLC resonant converter, such as Fundamental Harmonic Analysis (FHA) and Simplified Operation Modes (SOM), often ignore these parasitic capacitance parameters. However, experimental observations indicate that the presence of parasitic capacitance significantly affects circuits operating in either over-resonant or under-resonant states. Therefore, this paper proposed an accurate gain model for CLLC resonant converters considering the parasitic capacitance parameters of the switching transistors, as well as optimization of parameter design in the new model. For parameter design, the inductance ratio coefficient and characteristic impedance are employed, eliminating the need for iteration throughout the design process. Additionally, the paper investigates predetermined load conditions while satisfying gain objectives. The simulation has indicated the accuracy of the model.