Effect mechanism analysis of low-temperature on short-circuit robustness of SiC MOSFETs

The performance of SiC MOSFETs in practical operational environments is challenged by multifaceted stress scenarios, encompassing thermal, mechanical, and electrical stress, which significantly influence their reliability and operational longevity. Consequently, a comprehensive exploration of aging precursors and failure mechanisms becomes imperative for the SiC MOSFETs under diverse stress interactions. This study focused on the impact of low- temperature storage (LTS) on short-circuit (SC) ruggedness through direct current characteristic tests (DC test), low- frequency noise tests (LFN), and failure analysis (FA) for 1.2 kV SiC MOSFETs. The outcomes revealed that LTS stress adversely affected short-circuit withstand time (SCWT). These findings provide insights into the reliability and operational lifespan of SiC MOSFETs under real-world operating conditions.