A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors

This brief presents a double-data-rate (DDR) ripple counter with calibration circuits for correlated multiple sampling (CMS) in CMOS image sensors (CISs). This brief analyzes a specific type of least significant bit (LSB) error that obstructs the recording of the prior LSB count result during continuous counting processes when performing digital correlated double sampling (DDS) and digital CMS. This error stems from the transparent characteristic of the LSB in DDR counter and causes the increase of random noise. A calibration circuit is presented to calibrate the LSB error, which achieves carry propagation and retains the remainder by recording the result of the LSB after each quantization. The random noise is reduced by 25.5% based on simulation results in different CMS iterations after calibration. A $1280\times 1024$ prototype CIS is fabricated in a 110-nm 1P4M process. The experimental results show that at DDS mode, the CIS random noise is $147~\mu \text { V}_{\text {rms}}$ and ADC power consumption is $21.07~\mu $ W, whereas at CMS =2, the noise is $118~\mu \text { V}_{\text {rms}}$ and power consumption is $28.07~\mu $ W. In addition, the prototype CIS has a column FPN of 0.006%.