The Scalable Coherent Interface, IEEE P 1596, status and possible applications to data acquisition and physics

IEEE P 1596, the Scalable Coherent Interface (SCI) (formerly known as SuperBus), is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x), and other modern 32-b buses. SCI goals include a minimum bandwidth of 1 GB/s per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. Current directions are summarized, and the status of work in progress is reported. Some applications in data acquisition and physics are suggested.<>