A Combinational Logic Optimization Method for Large-Scale SFQ Circuits

This work aims to optimize the superconducting single flux quantum (SFQ) combinational logic synthesis process to cope with the scaling up of superconducting SFQ integration. The majority of current research is based on ABC logic synthesis methods, which do not support multioutput logic gates, including mapping dual data flip-flop, resettable D flip-flop with clear, and their variants. Therefore, in the combinational logic optimization stage, we propose a local optimization method to search for specific logic in Boolean expressions by performing the characteristic representation of matrices to achieve technology mapping for multioutput SFQ gates. Moreover, we use multioutput logic gates to replace the redundant logic in the circuit. We illustrate the operation of our approach on ISCAS benchmark circuits. By adopting our proposed methodology, the performance, power consumption, and area performance of SFQ circuits are improved, which also increases the efficiency of our cell library utilization.