Data-Aware 3-D TLC NAND flash Memory Reliability Optimization

The ever-increasing demand for high-density nonvolatile memory devices has led to the widespread adoption of 3-D triple-level cell (TLC) NAND flash memory. TLC NAND flash cut stored voltage levels into eight, shrinking the gaps between levels and dramatically impacting flash reliability. The high-density 3-D TLC flash structure increases the likelihood of data errors and cell-to-cell (C2C) interference becomes in three dimensions. The reliability is further degraded with every write/erase (W/E) cycle. However, the written data is the primary parameter in the reliability of many reliability threats. To this end, we utilize the state-of-the-art 3-D TLC NAND flash technology to characterize the impact of data on flash reliability experimentally. This work proposes a novel data-aware (DA) optimization technique to suppress errors in 3-D TLC NAND flash memory by improving the flash’s reliability based on page type, content, and technology. The technique exploits the data contents to suppress the degradation caused by every W/E cycle and mitigates the layer-to-layer variations by restructuring the data into a more reliable form. Such a technique aims to improve reliability and extend the lifetime of memory devices, making them more viable for high-reliability applications. Experimental evaluation shows that our technique can suppress the error bit count (EBC) by up to 60% and 45% on average over the nominal lifetime of the NAND flash, thereby improving flash lifetime by 55%, on average. Moreover, the technique can mitigate the layer-to-layer variations when spatially employed on specific layers, lowering EBC by 50%.