A 2-Tier TRL Calibration Technique to Assess Flip-Chip Interconnects at D-Band

In this paper we present a calibration technique to evaluate flip-chip technology performance at D-band frequencies. The method involves the addition of a (second-tier) Thru-Reflect-Line (TRL) calibration within the flip-chip to extract the complex two-port S-parameters of the individual interconnects on back-to-back coplanar-wave (CPW) structures on a fused silica substrate. The calibration quality can be achieved by the high fabrication and assembly accuracy of the flip-chip interconnects and the thin-film technology. In addition, the TRL based approach allows, without accuracy loss, to offset the calibration reference plane from the vertical transition one, thus minimizing the impact of radiation losses during the modeling step. The results obtained with this method are compared to (conventional) back-to-back CPW transitions and to full-wave simulation of the 3D model of the flip-chip stud bumps. The agreement among the measurements and simulations highlights the technique’s potential for flip-chip packaging design and assessment.