An Improved Architecture for a Fully Digital UHF RFID PIE-Stream Data Recovery Circuit

In UHF RFID systems conforming to the EPC-Gen2 standard, data from reader to tag is sent in a pulse-interval encoded (PIE) manner. Recovery of this data is an important first step towards establishing communication. A data frame may be sent at any time after a completed startup, and, hence, the receiver must be continuously active. Traditionally, an analog or digital circuit samples the incoming signal and performs the decoding by measuring the times between received pulses. In this contribution, we propose an improved method that relies on a partly asynchronous architecture. Decoding and pulse-interval measurements are performed by an emulated JK-FlipFlop that enables or disables a counter, and symbol decoding is realized by thresholding the counter values. This procedure results in a bitstream that can be further processed by an attached shift register for the following command processing. We evaluated our new architecture with an FPGA-based prototype of a UHF-RFID-based sensor system comprising a protocol processor and additional control logic. We show that our new structure can be used with a reduced clock frequency compared to a conventional sampling-based decoder. Also, the new structure allows for better integration with approaches such as On-Demand Clocking since it may start its own clock at the start of the data frame. The new decoder circuit was integrated into an ASIC with a conventional automated synthesis process. The functionality has been shown in a post-layout simulation.