A Contingent Decision Equalizer Using Analog-in-Time Processing for PAM-4 Wireline Receiver

This paper presents a new hybrid feedforward equalization technique that moves wireline receiver speed constraints from architectural limitations to circuit realization. This paves the way for continual data rate enhancement with improved circuit performance. The feedforward approach uses multi-stage mixed-mode signal processing to perform incremental equalization. To ensure reliable performance in advanced CMOS processes, time-domain analog signal processing is used. This choice also enables linear energy scaling with data rate and allows proportional power scaling with degree of equalization. A 3-tap realization of the receiver fabricated in 28 nm CMOS process achieved a data rate of 52 Gb/s with an efficiency of 1.0 pJ/b and BER below le-4 with moderate lSI.