A 4ps Resolution Capacitive-Tuned Delay Pulse Shrinking Time to Digital Converter

This paper presents a 12-bit Time-to-Digital Converter (TDC) that combines a pulse shrinking ring comprising an even number of inverting delay elements with a pulse-arbiter delay line. This innovative approach leverages the linearity of the pulse shrinking ring and the high-resoluttun capabilities of the pulse-arbiter delay line, resulting in a TDC with exceptional linearity and accuracy. With a resolution of 4ps, this TDC functions efficiently in a standard 0.18 µm CMOS technology, offering a Full-Scale-Range (FSR) of 36600 ps.