Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits

Modern neural network models consume a large proportion of power in matrix-vector multiplications. At inference time, the trained network parameters are constant and organized in matrices. Knowing the constant matrices in advance can significantly benefit hardware utilization, throughput and energy consumption of neural network implementations. This paper seeks to achieve hardware optimizations and reduce the computational cost of constant matrix multiplication by exploiting redundancies in sub-expressions common to several products and outputs. For FPGA implementation, our results show that the number of lookup tables can be decreased by up to 62% compared to a standard baseline version already optimized by vendor tools.