Efficient Hardware Design of Convolutional Neural Networks for Accelerated Deep Learning

The hardware design of Convolutional Neural Networks (CNNs) significantly accelerates deep learning tasks, providing substantial improvements in computational efficiency and real-time processing capabilities. This continuous improvement of hardware design enhances the speed of convolutional operations by optimizing resource utilization and energy efficiency. Consequently, CNNs become more accessible for deployment in resource-constrained environments, facilitating advancements in a wide range of applications, from image recognition to embedded systems. In this paper, we propose a novel hardware design for CNNs demonstrating enhanced efficiency and performance. The proposed method incorporates a shared convolutional unit shared between multiple kernel units. The proposed design leverages a meticulous allocation of hardware resources. The proposed method is implemented on the Aletra 10 GX FPGA using the VHDL language. The CNN accelerator showcases remarkable results, with resource utilization percentages ranging from 2% to 26.35%. Operating at a clock frequency of 120 MHz with an 8-bit fixed design precision, the proposed method achieves superior energy efficiency at 28.41 GOPS/W, outperforming existing approaches. Experimental results show that testing with the CIFAR-10 dataset demonstrates a remarkable accuracy of 98.79%. Additionally, the novel design has a lower occupied area than the existing ones. This hardware design promises significant advancements in CNN acceleration and offers a robust solution for applications demanding both resource efficiency and high accuracy.