A 30-39 GHz 3.1-3.4 NF 6.6 dBm IIP3 CMOS Low-Noise Amplifier with Post-Linearization Technique

This paper introduces a positive feedback post-distortion (PD) linearization technique. Using a weakly inverse auxiliary transistor, compensates for the third-order non-linear current in the input CG transistor, enhancing linearity and increasing overall first-order transconductance for improved gain. The introduced additional noise is minimal. Leveraging on-chip inductance between the auxiliary and cascaded Common Gate (CG) transistors, in resonance with circuit parasitic capacitance, further reduces noise and enhances linearity. A 30–39 GHz CMOS linear Low-Noise Amplifier (LNA) is designed using this technique, implemented in 65 nm CMOS technology with a compact area of 0.15 mm2, Operating at 1.2 V, it consumes 11.87 mW. The LNA achieves 12.3-12.7 dB gain, 3.1-3.4 NF, and 6.6 dBm IIP3 within this frequency range.