A 0.6-V 108-nW 100-kHz Sub-Threshold Delay-Locked Loop with Digital Linearization for Low-Power SAR ADC

This paper investigates the instability of low-power low-frequency charge-pump delay-locked loops (DLL) operating in sub-threshold for low-power SAR ADC. We show the charge leakage of the loop-filter capacitor during the long idle state of the phase detector causes the control voltage of the DLL to drift. Although the amount of voltage drift is insignificant, the exponential relation between the delay and control voltage of the delay stage operating in sub-threshold results in a significant change in the delay of the DLL, causing the DLL to oscillate. To combat this, we propose a counter-based sub-threshold DLL with digital linearization. The delay stages of the DLL are linearized using a digital-to-analog converter (DAC) with its bit weights set as per the characteristics of the delay stage such that the relation between the delay and control voltage of the compensated delay stage is linear. Designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V, the DLL locks to a 100 kHz 50% duty-cycle external reference at FF/-20°C, TT/27°C, and SS/60°C process/temperature corners and consumes 108.6 nW at TT/27°C. The proposed DLL offers the distinct characteristics of intrinsic stability, ultra-low power consumption, and excellent compatibility with technology.