An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems

As wireline communication links transition from 100 Gb/s to 200 Gb/s per lane, new and complex forward error correction (FEC) architectures have been proposed to achieve acceptably low bit error rates (BERs). It is essential to understand how these architectures impact link performance under various channel conditions. However, existing methods of post-FEC BER analysis are unsuitable for this application. To address this, we present a flexible platform for FPGA-accelerated post-FEC BER analysis of 200 Gb/s wireline systems. This platform can accurately demonstrate post-FEC BERs at the 10
^–12
level within a day of simulation time, a speed improvement of 10,000X over software-based simulation platforms.