Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization

This study introduces a pioneering method for the layout generation of analog circuits, specifically designed for RRAM computing circuits using the TSMC 40nm process. By focusing on area and wire optimization, we have managed to reduce the layout area by up to 28.6% and the wirelength by 45.3%, all while maintaining power consumption and accuracy at levels comparable to conventional approaches. The method leverages strategic guard ring placement and precise transistor spacing to optimize the layout efficiently. Our findings highlight the method's capacity to address the challenges in analog layout generation, offering a pathway to enhance memory computing systems. This work contributes to the broader field of computing circuit design, providing insights that could influence future approaches on RRAM compatible physical designs.