Edge-Triggered Bi-Directional Gated Delay Line Up-Down Counters

This paper presents area-efficient edge-triggered bi-directional gated delay line (BDGDL) thermometer up-down counters. The principle, operation, and design considerations of the proposed counters are detailed. An 8b positive edge-triggered DBGDL up-down counter is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.8 V. Simulation results show the counter performs both up-counting and down-counting correctly at FF/-20°C, TT/27°C, and SS/60°C. The number of transistors per stage of the proposed counter is 13 while that of its MUX/DFF counterpart is 40, a reduction of 67.5%.