10 Gbps Data-dependent Jitter Measurement Circuit for Authentication Over Lossy Wireline Channels

This paper presents a relative jitter measurement circuit for use in wireline authentication receivers. Design considerations and trade-offs are discussed for a 10 Gbps realization in a 28nm CMOS process. The results show high accuracy jitter measurements over different channel profiles, with the errors less than 1.25% of the bit period. Simulated power consumption indicates minimal overhead to adding the proposed jitter measurement circuit for authentication in a wireline receiver.