Multi-Residue Two-Step Incremental ADC

This paper introduces a novel multi-residue two-step incremental analog-to-digital converter (MR-IADC) designed to enhance accuracy. In this scheme, unlike in a conventional two-step IADC, the conversion residue stored on the last integrator of the modulator is extracted multiple times. This provides an additional degree of freedom, thereby improving the Signal-to-Quantization-Noise-Ratio (SQNR). In the first step, the circuit is configured as a 1
^st
order Incremental ADC followed by a novel decimation filter. The fine quantization is realized using a SAR ADC with a two-capacitor DAC (2C-SAR). The SAR ADC samples the conversion residue of the first stage multiple times. The 2C-SAR ADC is followed by a Zero-Order-Hold (ZOH) filter, and it functions as a noise-shaping SAR within one conversion cycle. Compared to the conventional two-step IADC, the multi-residue two-step incremental ADC (MR-IADC) achieves an 8 dB improvement in SQNR by sampling the residue 4 times, and a 13 dB for sampling 8 times. Simulation results and theoretical analysis verify the effectiveness of this structure.