A Low Power High-Voltage Floating Output Level Shifter with Asymmetric Delay Reduction

This paper presents a low power high-voltage (HV) floating output level shifter (LS) with less than 0.7ns asymmetric delay. By using short-pulse method in designing both LS core and HV ground circuit (HVSS), the whole circuit consumes only 23uA with a 2MHz input square-wave signal and 300fF load capacitance. Cascaded by a simple digital circuit with asymmetric delay reduction technique, the delay of LS is less than 2ns normally for both rising and falling edge. Compared with the conventional high voltage ground generation method, the proposed HVSS generator circuit can reduce the current consumption by over 80%. The whole circuit is simulated in a 180 nm Bipolar-CMOS-DMOS (BCD) technology with an output range from 36.5V to 40V. Results show its excellent performance in both power consumption and asymmetrical delay margin, which indicates that the proposed LS is suitable for low power high voltage output DC-DC converters.