Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme

This paper describes an magnetic tunnel junction (MTJ) based nonvolatile register configuration for persistent arithmetic operations in intermittent computing. In the proposed nonvolatile register, one bit of information is retained with the resistance value of one MTJ device and the reference MTJ device commonly shared for each bit. In addition to reducing the number of MTJ devices and the write energy required to save data, the simplification of the write current control circuit also reduces the circuit area. The performance evaluation using a 55nm CMOS/MTJ-hybrid process technology shows that the proposed nonvolatile register can reduce the energy required for data saving by up to 49%, as well as the circuit area by 39%, respectively, compared to the conventional configuration.