A 17 dB High Gain 65% PAE Wideband CMOS Integrated Power Amplifier Design in 180 nm Process for Wireless Power Transfer Applications

This paper presents the design of a high gain, high power added efficiency (PAE) wideband power amplifier (PA) in the standard 180nm CMOS process for wireless power transfer (WPT) applications. The proposed PA design utilizes a single stage common-source architecture, working in the ultra-wideband (UWB) frequency range (3.1 - 10.6 GHz). The amplifying stage utilizes a single NMOS transistor where the scaling factor of the transistor is optimized to generate the highest transconductance,
$g_{m}$
value, and thus maximize the available power gain from the transistor. An analysis and optimization of the scaling factor is also performed to generate the optimal balance between achieving a
$\text{high} \ g_{m}$
while also minimizing the insertion loss from the quality factor of the integrated on-chip inductor so that a higher overall gain can be achieved. The designed PA achieves a maximum gain of 17.4 dB at 6.5 GHz frequency and the
$P_{1dB}$
compression point occurs at an input power of 7 dBm. In addition, a
$-3\mathbf{dB}S_{21}$
gain bandwidth of 2.19 GHz (5.29 - 7.48 GHz) can be obtained from the proposed PA design. At the
$P_{1dB}$
compression point, the PA is able to generate an output power of 24.4 dBm at 6.5 GHz frequency for 3.3 V drain supply voltage. The proposed PA is able to achieve a peak PAE performance of 65.6% at the 16 dBm input power. By employing a single stage L-shaped shunt inductor and series capacitor as part of the input and output matching network,
$> 60\%$
PAE performance is achieved over a wide bandwidth of 2 GHz from 5.5 - 6.5 GHz.