Challenges and Opportunities in Heterogenous Integration During Design and Process Co-Optimization

In the process of seeking more efficient form factors for electronic devices that meet power, performance and latency requirements, heterogenous integration has risen to become one of the most promising areas to meet the demand of new products that meet very strict cost, performance, latency and power requirements. Whereas traditional board integration of different components meets cost requirements, it does not meet performance and/or latency requirements. In the same manner Systems-On-Chip (SOCs) may meet performance and form factor requirements but not cost. By increasing the complexity in which silicon dies are integrated together, it may be possible to deliver unique functionality at lower cost and faster time to market. As the manufacturing complexity increases, Design flows must be updated to accommodate a large variety for techniques allowing wiring redistribution, 2.5D interposers, 3D stacking, Plasma dicing, and Through Silicon vias (TSVs). In this work, we focus on the parallels between semiconductor processes and packaging processes, and outline a possible path to enhance heterogeneous packaging operations with techniques developed in semiconductor manufacturing.