A Generalized Multi-Level Structure for High-Precision Binary Decoders

Binary decoders are ubiquitous in digital circuits for computing, particularly within memory addressing, multiplexing, and demultiplexing. A commonly used method for constructing binary decoders is the coincident row-column structure, which uses two smaller decoders intersecting over an array of AND gates to generate the output of the decoder as a whole. While this structure works for the typical sizes of modern computers (under 128 bits), it still has room for improvement, especially at high precisions, such as 1024 bits and greater. This work proposes three multi-level architectures for binary decoders suitable for high-precision inputs, generalizing the existing row-column decoder architecture. We compare our novel structure to the aforementioned row-column method, a tree-based structure, and other single-level decoder constructs. Then, we analyze critical path (or delay) and complexity (or cost, in terms of lookup tables or transistors) as a function of input precision. Finally, we recommend decoder architectures for different input precisions and implementation technologies (FPGA or ASIC).