An Automatic Calibration Method Applied to the VDL Delay Chain of MVT Chip

The Multi-Voltage Threshold (MVT) method is an approach to digitizing scintillation pulses by sampling a set reference voltage. This method has been demonstrated to be effective for Positron Emission Tomography (PET) systems under field programmable gate array (FPGA). To enhance integration and reduce system costs, we designed an 8-channel MVT22 chip using application specific integrated circuit (ASIC) technology, capable of achieving a bin size of 19.5 ps. However, due to consistency issues between different channels, we propose a method for automatic on-chip calibration of the Vernier delay line (VDL) measurement for the MVT22 chip. The performance before and after calibration have been evaluated and the results indicate a significant improvement in the consistency of VDL distribution among channels after chip calibration. On average, in homogenous tests, the standard deviation is reduced to 28.3 ps, with an optimization of approximately 4.4 ps, and full width at half maxima (F WHM) is reduced to 50.6 ps with an optimization of approximately 14 ps. In heterogeneous experiments, the standard deviation is reduced to 27.9 ps, with an optimization of approximately 5.9 ps, and FWHM is reduced to 56.6 ps with an optimization of approximately 7.8 ps.