Development of an 18-Picosecond Resolution, 64-Channel TDC, embedded in a Xilinx Field-Programmable Gate Array

Time-to-Digital Converters (TDCs) play a critical role in numerous high-precision applications across the fields of nuclear science, biomedical engineering, and digital communication systems, including Time-of-Flight (ToF) ranging, Positron Emission Tomography (PET), and All-Digital Phase-Locked Loops (ADPLLs). The demand for flexible architectures providing higher timing precision for an increased number of channels has become a focal point due to the limitations of traditional single-channel TDCs which suffer from low bitrate and resolution. This paper presents the design, implementation and commissioning of a 64-channel TDC using the latest Xilinx Field-Programmable Gate Array (FPGA) technology, aimed at overcoming these challenges and significantly enhancing measurement capabilities. The design is based on a combination of Tapped Delay Line (TDL) and Coarse Counter techniques to optimize both precision and dynamic range. The implementation achieved a remarkable temporal resolution of 18 picoseconds in an exemplary multi-stop implementation providing a sequence of nine time stamps in each cycle. This paper details the system architecture, the implementation challenges and the performance evaluation.