Paralleling 3.3-kV/800-A rated SiC-MOSFET Modules: An Optimization Method

When power semiconductor modules are connected in parallel, the switching characteristics and current imbalance of each device need to be aligned. This paper focuses on the mutual inductance between the gate driver and the main circuit and the stray inductance of the main circuit when a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) module with a rating of 3.3 kV/800 A is operated in parallel, to examine the effect on the switching operation and describe the optimum method. First, the effect of mutual inductance between the gate wiring of devices in parallel and the main circuit was evaluated by performing actual measurements, and it was shown that gate voltage fluctuations could be suppressed by bringing the gate wiring of each device closer together. Next, when an external capacitor C(gs) was inserted as a gate-noise countermeasure, it was shown that reducing the loop between the main circuit and the capacitor could decrease the mutual inductance and lessen the difference in switching characteristics. Finally, the difference in stray inductance of the main circuit of each device was evaluated. Differences in stray inductance of the main circuit cause current imbalance, resulting in differences in the loss of each device. As a result, there is a difference in the thermal fatigue life of each device, and the expected life of the system is shorter than anticipated. It is therefore important to match stray inductances of the main circuits within the range where turn-off surges are allowed.