Ph.D. Project: Compiler-Driven Hardware/Software Co- Design for Embedded AI

Ahstract- The increasing computational complexity of AI work-loads has led to the introduction of numerous accelerator archi-tectures. However, these designs often neglect the software tooling necessary to generate optimized mappings. Additionally, future compute architectures are expected to become more heteroge-neous, resulting in additional challenges regarding mapping of tasks to compute units. In this Ph.D. project, a novel methodology to generate compilers with an optimization pipeline for custom hardware accelerators is presented. The foundation of the work is a new Architecture Description Language (ADL) used to capture architectural details necessary for the compilation process. Based on this, simulators on both core and system level are generated that assists in the design of the underlying hardware. Finally, to assist with compilation, a flow to automatically register the new hardware design to a retargetable compiler will be designed. For the optimization pipeline, we focus on two specific aspects: Tensorization to map instruction sequences to the accelerator, and automated scheduling to optimize the execution time and energy.