Ph.D. Project: Optimizing the Data Traffic for Large Graph Processing on FPGA via a Stateful Approach

Real-world graph size increases rapidly and often exceeds the capacity of the FPGA device, incurring memory over- subscription and performance degradation. Existing approaches ignore the support for hyper-scale graphs and cross-iteration acceleration. In this work, we propose SoGraph, a processing architecture for out-of-FPGA-memory graph acceleration on FPGAs, cooperating with the host. To minimize data transfer during the processing, $w$e adopt a lightweight stateful hardware extension and an activeness-driven subgraph scheduler in the edge-centric processing pipeline for graph working set pruning. A preliminary experiment shows that our prototype achieves 5.63x performance speedup over the modified state-of-the-art design.