Power and Stability Optimization of High Performance SRAM Cell Using Jaya Algorithms for Low Power Drone

Static random access memory (SRAM) is a widely used type of core memory element of processors to store data in industrial and drone applications. We suggest a static RAM (SRAM) model with the 16-nm feature size node technology based on graphene nanoribbon (GNR) field-effect transistors (GNRFETs), which is optimized technology based on the trade-off through performance, stability, and power consumption. The natural cubic spline-guided novel Jaya method (S-Jaya), a unique model-free solution approach, is proposed in this study for effectively handling the optimization of six-transistor (6T) SRAM cells under process fluctuations. Consider an SRAM cell that stores one bit at its operational voltage. The S-Jaya lacks algorithm-specific deterministic parameters, just like the general Jaya algorithm. The iterative search technique incorporates an ordinary-based cubic spline-technology calculation model to help update candidate solutions (operation settings of voltage) for the S-Jaya, and this addition has the potential to enhance SRAM cell performance. The efficiency of the suggested S-Jaya algorithm is improved and addresses optimization problems while taking into consideration a range of process variation situations and is validated through simulation studies and testing. To show the proposed algorithm's benefits, its performance is compared to that of the generic Jaya and the widely used particle swarm optimization (PSO) in the model-free MPPT. The suggested S-Jaya algorithm converges more quickly and offers a higher overall SRAM cell efficiency, according to the results of simulated studies and experiments.