A Dual-Mode Split-Based Calibration Technique for Time-Interleaved ADCs

This paper proposes a structure of spilt ADC which can be converted to a Time interleaved (TI) sampling mode to double the sampling rate. The architecture has two modes. In the split mode, two channels use the same clock, and through the split architecture the capacitor mismatch error, amplifier gain error, and timing skew are calibrated. After calibrate those nonideal factors, the TI mode is started. By shifting the phase of one clock 180-degree, the sampling rate is doubled. The architecture greatly reduces the complexity of the calibration algorithm and hardware consumption of time-interleaved ADC. The behavioral simulation shows llbit split ADC can be converted to TI ADC with double sampling rate which achieves 58dB SNDR, 78dB SFDR on average.