Enhanced DSP Blocks for Full High-Definition Video Bridging Application on FPGAs

FPGA chips are widely used in video bridging applications. The DSP (Digital Signal Processing) in FPGA can effectively improve the efficiency of video image processing algorithms. The 10 bits of pixel depth is common for Full High-Definition (FHD). However, in the existing commercial FPGAs, the DSP does not naturally support 10x10 multiplication. This brings some waste in area and power consumption. This paper proposes a new architecture of embedded DSP. It increases the maximum number of 10x10 multiplications in a DSP block to 8. It is also compatible with common working modes such as multiplication (18x18, 18x9), and accumulation. Meanwhile, introduce power gate and clock gate units in the DSP block to achieve fine-grained control of the power consumption. Users can dynamically control the power supply through their own logic. The entire circuit was successfully designed and implemented in an industrial 22nm process. The experimental results show that the static power consumption of the DSP block is about 20uW, the dynamic power consumption is about 200uW. And the maximum operating frequency can reach 670MHz. The effective area utilization of our DSP in 10x10 mode is 2.2 and 2.5 times higher than that in Intel Arria 10 series and Xilinx UltraScale series FPGAs, respectively.